(1) Field of the invention
The present invention relates to a timing control device, more particularly to a timing control device for providing a color signal to a data driver integrated circuit having an improved single bank configuration.
(2) Description of the Related Art
Generally, a liquid crystal desplay (LCD) module includes a plurality of gate lines and source lines. An LCD module includes: an LCD panel with switching transistors and pixels which are formed at the cross point of each gate lines and source lines; a gate driver which applies a turn-on voltage to the respective gate lines sequentialy; a data driver (also called `source driver`) which applies a gray voltage to the source lines corresponding to a color signal; a timing controller which outputs a control signal and a color signal for driving the gate driver and the data driver after receiving a vertical synchronizing signal, a horizontal synchronizing signal, and a color signal from a graphic controller outside of the LCD module; a voltage generator which generates gate turn-on and turn-off voltages and a common voltage to be applied to the gate driver; and a gray voltage generator which generates a gray voltage to be applied to the data driver.
In the LCD module as described above, the data driver includes a plurality of source driver ICs and the gate driver includes a plurality of gate driver ICs. The data driver IC is provided with a plurality of shift registers for storing inputed color signals by 1 bit for each source line. For example, if a data driver IC covers fifty source lines of the LCD panel, each of the data driver ICs includes fifty shift registers which are connected serially.
There are conventionally two types of the data driver IC array, that is, a dual bank and a single bank.
In the dual bank, data driver ICs are arrayed on both parts of the LCD panel, upper or lower, such that the ICs of one part cross over the ICs of the other part and the source lines in odd number (or even number) are connected to the upper data driver ICs and the source lines in even number (or odd number) are connected lower data driver ICs.
In the single bank, the data driver ICs are serially arrayed on either upper or lower part of the LCD panel.
FIG. 1 shows an LCD of conventional dual bank.
In FIG. 1, PC-SET 11 IS a graphic controller which generates control signals and data signals, wherein the control signals include a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enabling signal DE, and a main clock signal MCLK, and the data signals include an even numbered data DATA.sub.-- EVEN and an odd numbered data DATA.sub.-- ODD.
An interface device 12 controls driver circuits 13, 14 and 15 according to the control signal and the data signal from PC-SET 11. An upper data driver circuit (UP SOURCE IC) 14 of the interface device 12 outputs even numbered data (DATA.sub.-- EVEN) and the lower data driver circuit (DOWN SOURCE IC) 15 outputs odd numbered data (DATA.sub.-- ODD). An LCD panel 16 is operated by a gate drive circuit 13 and the upper and lower data driver circuits 14 and 15.
In a dual bank LCD, the upper data driver ICs are connected with each other such that color data may be shifted in serial mode, and the case is same for the lower data driver ICs. For example, in a dual bank data driver with 800 source lines and 8 data driver ICs which covers 100 source lines, two sets of four data driver ICs are arrayed on both parts of LCD panel and connected with each other cross-wise. The upper four data driver ICs have a structure wherein an output terminal of the last shift register of a preceding IC is connected with an input terminal of initial shift register of current IC. The case is same for lower four data driver ICs.
In case of a single bank data driver with same source lines, eight data driver ICs are serially arrayed on either upper or lower part of the LCD panel and an output terminal of the last shift register of a preceding IC is connected with the input terminal of initial shift register of current IC.
A timing controller in the dual bank has also different structure and function from the same in the single bank. For example, when a color signal with the single bank data array is inputted in a graphic controller, the timing controller in the dual bank arrays each color signals from the graphic controller, dividing the signals into an odd part and an even part and transmitting respectively to the upper data driver ICs and lower data driver ICs of the data driver. However, in case of a single bank timing controller, the dividing process is not necessary.
In a dual bank data driver, both color signals of even number and odd number from the timing controller are inputted simultaneously to upper data driver ICs and lower data driver ICs.
Therefore, in the dual bank data driver, the upper data driver ICs and lower data driver ICs simultaneously drive every source lines of the LCD panel. On the other hand, in the single bank data driver, either upper or lower data driver ICs transmit signals to every source lines of the LCD panel.
If a sustaining period of a data pulse which is inputted to the source line in the dual bank is equal to a sustaining period in the single bank, a driving period of the source line in the single bank data driver is two times of that in the dual bank data driver. Therefore, in order to adjust driving periods to be equal, the operating frequency of the single bank data driver should be twice as much as that of the dual bank data driver.
Generally, the higher is the operating frequency, the more electromagnetic interference (EMI) occurs. Therefore, the single bank data driver is not so useful as the dual bank data driver in view of the operating frequency.
A graphic system for eliminating the EMI was disclosed in Korean patent application no. 95-49696, wherein a carry signal of lower frequency than the main clock signal has been used in stead of the main clock signal.
However, as the data driver ICs are arrayed on both parts of the LCD panel, the dual bank data driver occupies more area in LCD module than the single bank data driver. The single bank data driver is more useful than the dual bank data driver in that it enables further compact design of the LCD panel. Along with currently widespread use of notebook computer, this compactness of the single bank data driver becomes highlighted. And there is increasing requirement of developing LCD driver with a reduced operating frequency and an improved compactness.